Research

Along the past few years, the covered research interests have been focused in the following three orthogonal research directions:

  • Computer architectures and dedicated processing structures
    Focus:
    Specialized computational architectures
    Homogeneous multi-processor structures
    Heterogeneous multi-core processing structures
    Applications:
    Video coding
    Biological sequences analysis
  • Embedded systems design and implementation
    Focus:
    System reliability
    Low-power implementations
    Applications:
    Biomedical
    Control
    Signal processing
  • Digital signal processing algorithms
    Focus:
    Video coding and transcoding
    Image processing
    Applications:
    Video-conferencing
    Video-surveillance
    Multimedia signal processing


Research Networks:

Network:
HiPEAC: European Network of Excellence on High Performance and Embedded Architecture and Compilation
(Affiliate Member)

Financial Support:
European Seventh Framework Programme (FP7).
Duration:
2004 - 2015
Description:

HiPEAC is a Network of Excellence funded by the Computing Systems research objective of the European FP7-ICT program. Due to technology limitations, the domain of high-performance processors is experiencing a radical shift towards parallelism through on-chip multi-cores and chip customization, leading to heterogeneous multi-core systems.
The objectives of HiPEAC are to ensure the visibility of European institutions in the high performance embedded market, and to promote the integration of research efforts in a common direction. Such objectives have been attained by:
 - Promoting the coordination of researchers from industry and academia interested in the topic of the cluster;
 - Stimulating joint research between member institutions, across the different disciplines: computer architects, design tool builders, compiler builders, system designers, between researchers from academia and industry, between European and non-European institutions;
 - Stimulating the impact of research results in the form of highly visible publications and commercialization of research results by existing companies or by newly created companies.
The ultimate goal is to further increase Europe’s worldwide visibility in the HiPEAC domain and to help companies to achieve world-leading positions in the computing systems and computing products.


Network:
ComplexHPC: Open European Network for High Performance Computing on Complex Environments (ICT COST Action IC0805)
(Research Member)

Financial Support:
European Cooperation in Science and Technology (COST) programme, under the Information and Communication Technologies (ICT) domain, in the scope of WG4: applications of hierarchical-heterogeneous systems.
Duration:
2009/01/08 - 2013/05/06
Description:

In different fields of science and engineering it is necessary to solve complex and challenging problems with high computational cost. For this purpose, scientists and engineers normally use homogeneous high performance computers. Nowadays, the emergence of heterogeneous computing allows research groups, enterprise and educational institutions to use networks of processors which are already available. On the other hand, high performance computers have become more and more hierarchical and heterogeneous (e.g., a cluster of multiprocessor nodes using multicore processors). These modern hierarchical and heterogeneous computing infrastructures are hard to program and use efficiently, particularly for extreme-scale computing. Consequently, none of the state-of-the-art solutions are able to efficiently use such environments.
The main objective of this project is to develop an integrated approach for tackling the challenges associated with heterogeneous and hierarchical systems for High Performance Computing.
As a result of this Action, an European research network, focused on high performance heterogeneous computing will be established, in order to address the whole range of challenges posed by these new platforms including models, algorithms, programming tools and applications.


Network:
SeqAhead: Next Generation Sequencing Data Analysis Network (BMBS COST Action BM1006)
(Research Member)

Financial Support:
European Cooperation in Science and Technology (COST) programme, under the Biomedicine and Molecular Biosciences (BMBS) domain, in the scope of WG3: software.
Duration:
2011/01/17 - 2015/03/17
Description:

Next generation sequencing (NGS) is a highly parallelised approach for quickly and economically sequencing new genomes, re-sequencing large numbers of known genomes, or for rapidly investigating transcriptomes under different conditions. Producing data on an unprecedented scale, these techniques are now driving the generation of knowledge (especially in biomedicine and molecular life sciences) to new dimensions. The massive data volumes being generated by these new technologies require new data handling and storage methods. Hence, the life science community urgently needs new, and improved approaches to facilitate NGS data management and analysis.
This COST Action unites bioinformaticians, computer scientists and biomedical scientists, harnessing their expertise to bring NGS data management and analysis to new levels of efficiency and integration. Rigorous surveillance of NGS technology and NGS-related software developments will allow the partners to generate software solutions for future NGS opportunities in a timely manner. The Action will increase the ability of European groups to maximally benefit from NGS technology, and will create a nucleus for world-wide activities to jointly address the upcoming biomedical informatics revolution.



Projects:

Title:
THREadS: Multitask System Framework with Transparent Hardware Reconfiguration
(Research Member)

Financial Support:
FCT Project PTDC /EEA-ELC /117329/2010
Duration:
2012/01/01 - 2014/12/31
Description:

The THREadS project proposes the development of a framework for reconfigurable computing systems based on the following characteristics:
 - the invocation of the reconfigurable processing units (RPUs) is completely transparent to the programmer; he does not require to know if a given call to a library function is executed in the general purpose processing unit (GPPU) or in an RPU;
 - the system allows multiple tasks to share RPUs;
 - the user can download a highly optimized core from an online RPU store and install it on the system, just as he can install a new library in a personal computer;
 - the framework includes a set of pre-developed hardware and software interface modules that eases the development of new RPUs by hiding the complexity to interface the remaining system (GPPU, memory, etc);
 - each RPU acts as an independent processing core able to fetch data directly from memory, thus allowing the GPPU to continue processing other threads.


Title:
HELIX: Heterogeneous Multi-Core Architecture for Biological Sequence Analysis
(Principal Investigator)

Financial Support:
FCT Project PTDC/EEA-ELC/113999/2009
Duration:
2011/01/01 - 2013/12/31
Description:

HELIX project aims at the development of integrated and parallel hardware and software platforms targeting the acceleration of a wide range of bioinformatic algorithms. It exploits new Single Program Multiple Data (SPMD) parallel processing strategies to accelerate several algorithms related to DNA re-sequencing, Multiple Sequence Alignment (MSA) and gene finding. Such approach will be supported with the development and implementation of a highly efficient and flexible programmable multi-core parallel architecture, in order to speedup the execution of the most demanding computational kernels that are shared by these applications
These objectives will be attained by an integrated research on several distinct domains, such as the design of dedicated heterogeneous multi-core processing structures; the development of an optimized memory hierarchy, based on a Distributed Shared Memory (DSM) organization with a Non Uniform Memory Access (NUMA) between the several cores of this structure; the design of a dedicated Network On-Chip (NOC) communication infrastructure, to allow fast and concurrent communications between all the included cores; the development of efficient inter-chip communication mechanisms to allow the aggregation of several of these multi-core structures, in order to scale and further improve the offered processing throughput; and the conception of a software development framework, to simplify the programming of the proposed multi-core architecture and to confer portability with already existing implementations.


Title:
TAGS : The power of the short - Tools and Algorithms for next Generation Sequencing applications
(Research Member)

Financial Support:
FCT Project PTDC/EIA-EIA/112283/2009
Duration:
2011/01/01 - 2013/12/31
Description:

TAGS project aims at developing new algorithms an tools for next generation DNA sequencing applications. Such challenges will be addressed by developing accurate error models, approximate indexing methods, distributed data structures and exploiting multi-core system architectures.
The adoption of precise error models will allow to accurately model the types of errors that are inherent to HTSR technologies. Then, approximate indexing methods will be used to pre-process the reference genome and filter out large fractions of the genome where the reads cannot possibly match. Parallel processing platforms will be extensively exploited to accelerate the alignment. The development of an integrated parallel programming framework will allow the simultaneous exploitation of three levels of parallelism: 1) Coarse-grained, by dividing the sequence database in subsets that will be assigned to each processing node of a cluster/grid; 2) Intermediate-grained, by tiling the sequence pair alignment procedure in several chunks that are individually processed by the cores available in each multi-core processing node; 3) Fine-grained, by following the Single Instruction Multiple Data (SIMD) paradigm to simultaneously evaluate several neighboring partial scores of the alignment procedure between the query sequence and the reference genome.
When combined together, its is expected that the indexing methods and the parallel architectures will make it possible to obtain a re-sequencing platform that is competitive in international terms.


Title:
IDEA: Integrated Design for Automation of Anaesthesia
(Research Member)

Financial Support:
FCT Project PTDC/EEA-ACR/69288/2006
Duration:
2007/01/01 - 2010/12/31
Description:

Project IDEA aims at the development of an Autonomous Integrated System for the Automation of Anaesthesia. This will provide a computational platform for clinical testing, both in animal and human patients, that will form a significant step towards reliable automation of anaesthesia, both from the technological and scientific standpoints.
In particular, the SiPS research team will be responsible for the specification, assembly and installation of the hardware platform of the integrated system. This platform will consist of an autonomous unit with two processing boards, one dedicated to control and the other to supervision. The processing board dedicated to the control will be based on a high-performance processor that supports high-precision floating-point computations. The supervision board will be based on a general purpose processor, able to gather data and information directly from the sensors and from the processing board dedicated to control. This last processing board can dynamically change processing parameters for the control, according to the gathered information. The sampling rate will be of the order of a few seconds (typically 5 seconds for DoA and 20 seconds for neuromuscular blockade). The whole unit will have to comply with the applicable standards for electrical equipment.


Title:
AMEP: Adaptive H.264/AVC Motion Estimation Processor for Mobile and Battery Supplied Devices
(Research Member)

Financial Support:
FCT Project POSI/EEA-CPS/60765/2004
Duration:
2005/01/01 - 2008/11/30
Description:

The main goal of this research project is the development of a new motion estimation algorithm suitable for mobile and battery supplied devices. To develop this new algorithm, based on a modified block matching processing scheme, an optimized processing core and several enhancements and optimizations to the search strategy will be considered, so as to adapt it to the intrinsic characteristics of video signals and target application devices. The improvements will consider the movement of the terminal in the prediction of the candidate motion vector to reduce the set of search candidates and dynamic adaptation to the current motion field pattern of the target application (e.g. enhancing the resolution of the search in the inner area for video-conference like applications). Moreover, the estimation procedure will also be dynamically adjusted to the terminal battery resources using efficient power management techniques such as computational budgets for arithmetic operations, reduction of the precision level and tuning of the clock frequency.
A dedicated architecture will be designed to implement the optimized ME algorithm in an ASIC device to be embedded as a co-processor in video coding systems, for which a standard cell library for deeper sub-micron technology (e.g. CMOS 0.18µm technology process) will be used. To carry out this objective, the long term experience of the research team in the development of specialized processors will be an invaluable advantage.
As an outcome of the research project, the developed ME processor will be made available as an intellectual property protected core.


Title:
COSME: Configurable Structures for Motion Estimation
(Research Member)

Financial Support:
FCT Project POSI/40877/CHS
Duration:
2002/01/14 - 2004/01/14
Description:

The main goal of this research project is the development of a new class of fully parameterizable multiple array VLSI architetures and dedicated processors for motion estimation in video sequences, based on the full search block matching (FSBM) algorithm. This class combines both pipelining and parallel processing techniques and is based on a new efficient type I single array architecture with minimum latency, maximum throughput and full utilization of the hardware resources. It provides also the ability to configure the target processors according to the setup parameters, the processing time and the circuit area specified limits, making it possible to adapt the implementation to the target technology (e.g. FPGA, ASIC, etc.). In order to attain real time processing, new fast arithmetic units should also be developed to perform a set of basic operations such as addition, subtraction and absolute value computation.
Based on the proposed architectures and arithmetic units, a dedicated integrated circuit for motion estimation may be developed, by making use of a standard cell library for a CMOS - 0.25µm technology process. From the preliminary results, it is possible to conclude that the circuit is able to perform motion estimation in real time on high resolution image sequences. As an example, video sequences in the 4CIF format (576 x 704) can be processed at a rate of about 16 images per second.


Title:
Sistema de Modelação e Processamento de ECG de Alta Definição
(Research Member)

Financial Support:
FCT Project PRAXIS/PSAU/C/SAU/24/96
Duration:
1997/06/01 - 1999/12/01
Description:

The main goal of this research project is the development and implementation of a new high definition ECG modeling and analysis system, based on the use of archetypal analysis for the study and interpretation of ECG signals. The complex system formed by the autonomous nervous system and the heart is modeled as a modulation system, where the first generates the signal that modulates a sequence of pulses which excite the heart. Such decomposition corresponds to the usual study of the heart rate variability and of the high resolution electrocardiography. The adopted archetypal analysis approach allows the estimation of some archetypes (or prototypes) of the heart beats or, if required, of the P, QRS and T wavelets. This methodology is achieved through the use of new algorithms to segment the original ECG signal, providing "clean" waves and good estimates of the "noise". In parallel, the independent component analysis is also performed, as well as the decomposition with the wavelet transform.



Prototypes:

As a result of the research conducted in the last few years, the following prototypes have been developed and made publicly available:



Journal Collaborations:

Along the past few years, Nuno Roma has collaborated with several editorial committees of renown international journals:

Conference Collaborations:

Along the past few years, Nuno Roma has participated in several conference committees and integrated the reviewing committees of several international publications:

  • Organizing committee memberships:
    ARC'2016 - International Symposium on Applied Reconfigurable Computing, Rio de Janeiro, Brazil, March 21 - 24, 2016.
    ISCAS'2015 - IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 24 - 27, 2015.
    CERN'2015 - 2015 CERN Spring Campus, Lisbon, Portugal, April 1 - 3, 2015.
    EUSIPCO'2014 - 22nd European Signal Processing Conference, Lisbon, Portugal, September 1 - 5, 2014.
    TRUDEVICE'2014 - Training School on Trustworthy Manufacturing and Utilization of Secure Devices, Lisbon, Portugal, July 14 - 18, 2014.
    ISPDC'2009 - 8th International Symposium on Parallel and Distributed Computing, Lisbon, Portugal, June 30 - July 4, 2009.
  • Workshops and special sessions organization:
    OPTIM'2016 - International Workshop on Optimization of Energy Efficient HPC & Distributed Systems, as part of the International Conference on High Performance Computing & Simulation (HPCS'2016), Innsbruck, Austria, July 18 - 22, 2016.
    PPEO'2016 - International Workshop on Performance, Power and Energy-Efficiency Optimization in Heterogeneous Systems, as part of the 12th International Meeting on High Performance Computing for Computational Science (VECPAR'2016), Porto, Portugal, June 27 - July 1, 2016.
    AASC'2015 - International Workshop on Architecture-Aware Simulation and Computing, as part of the International Conference on High Performance Computing & Simulation (HPCS'2015), Amsterdam, The Netherlands, July 20 - 24, 2015.
    ISCAS'2015 - Special Session on "Efficient Circuits and Systems for HEVC and its 3D Encoding Extension", as part of the IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 24 - 27, 2015.
  • Program committee memberships:
    CETC'2016 - Conference on Electronics, Telecommunications and Computers, Lisbon, Portugal, December 6-7, 2016.
    HPCS'2016 - International Conference on High Performance Computing & Simulation, Innsbruck, Austria, July 18-22, 2016.
    REC'2016 - XII Jornadas sobre Sistemas Reconfiguráveis, Universidade de Trás-os-Montes e Alto Douro, Vila Real, Portugal, June 20-21, 2016
    LP-EMS'2016 - 2nd Workshop on design of Low Power EMbedded Systems - co-located with ACM International Conference on Computing Frontiers, Como, Italy, May 16-18, 2016.
    EEHCO'2016 - 2nd HIPEAC Workshop on Energy Efficiency with Heterogeneous Computing, Prague, Czech Republic, January 18-20, 2016.
    HPCS'2015 - International Conference on High Performance Computing & Simulation, Amsterdam, The Netherlands, July 20-24, 2015.
    REC'2015 - XI Jornadas sobre Sistemas Reconfiguráveis, Universidade do Porto, Porto, Portugal, February 5-6, 2015
    EEHCO'2015 - HIPEAC Workshop on Energy Efficiency with Heterogeneous Computing, Amsterdam, The Netherlands, January 19, 2015.
    EUSIPCO'2014 - 22nd European Signal Processing Conference, Lisbon, Portugal, September 1 - 5, 2014.
    ICME'2014 - IEEE International Conference on Multimedia & Expo, Chengdu, China, 14-18 July, 2014
    REC'2014 - X Jornadas sobre Sistemas Reconfiguráveis, Universidade do Porto, Vilamoura, Portugal, April 13, 2014
    ICME'2013 - IEEE International Conference on Multimedia & Expo, San Jose, California, USA 15-19 July, 2013
    IPDPS'2013 (PhD Forum) - IEEE International Parallel & Distributed Processing Symposium (PhD Forum), Boston, Massachusetts, USA 20-24 May, 2013
    REC'2013 - IX Jornadas sobre Sistemas Reconfiguráveis, Universidade de Coimbra, Coimbra, Portugal, 7-8 February, 2013
    ICME'2012 - IEEE International Conference on Multimedia & Expo, Melbourne, Australia, 9-13 July, 2012
    REC'2012 - VIII Jornadas sobre Sistemas Reconfiguráveis, Instituto Superior de Engenharia de Lisboa, Lisboa, Portugal, 9-10 February, 2012
    ICME'2011 - IEEE International Conference on Multimedia & Expo, Barcelona, 11-15 July, 2011
    REC'2011 - VII Jornadas sobre Sistemas Reconfiguráveis, Faculdade de Engenharia de Universidade do Porto, Portugal, 3-4 February, 2011
    ICME'2010 - IEEE International Conference on Multimedia & Expo, Singapore, 19-23 July, 2010
    REC'2010 - VI Jornadas sobre Sistemas Reconfiguráveis, Universidade de Aveiro/IEETA, Portugal, 4-5 February, 2010
    REC'2009 - V Jornadas sobre Sistemas Reconfiguráveis, Universidade Nova de Lisboa, Portugal, 5-6 February, 2009
    JETC'2008 - IV Jornadas de Engenharia de Electrónica e Telecomunicações e de Computadores, ISEL, Lisboa, Portugal, 20-21 November, 2008
    REC'2008 - IV Jornadas sobre Sistemas Reconfiguráveis, Universidade do Minho, Braga, Portugal, 7-8 February, 2008
    ICME'2007 - IEEE International Conference on Multimedia & Expo, China, 2-5 July, 2007
  • Reviewing committee memberships:
    International Conferences:
    ESA'2014 - 22nd European Symposium on Algorithms, Wrocław, Poland, September 8 - 10, 2014.
    EUSIPCO'2014 - 22nd European Signal Processing Conference, Lisbon, Portugal, September 1 - 5, 2014.
    TSP'2014 - IEEE International Conference on Telecommunications and Signal Processing, Berlin, Germany;
    ICME'2014 - IEEE International Conference on Multimedia & Expo, Chengdu, China, 14-18 July, 2014
    REC'2014 - X Jornadas sobre Sistemas Reconfiguráveis, Universidade do Porto, Vilamoura, Portugal, 13 de Abril, 2014
    ICCES'2013 - IEEE International Conference on Computer Engineering and Systems, Cairo, Egypt;
    SBCCI'2013 - Symposium on Integrated Circuits and Systems Design, Curitiba, Brasil;
    TSP'2013 - IEEE International Conference on Telecommunications and Signal Processing, Rome, Italy;
    ICME'2013 - IEEE International Conference on Multimedia & Expo, San Jose, California, USA 15-19 July, 2013
    IPDPS'2013 (PhD Forum) - IEEE International Parallel & Distributed Processing Symposium (PhD Forum), Boston, Massachusetts, USA 20-24 May, 2013
    ICCES'2012 - IEEE International Conference on Computer Engineering and Systems, Cairo, Egypt;
    SPIRE'2012 - International Symposium on String Processing and Information Retrieval, Cartagena de Indias, Colombia;
    EUSIPCO'2012 - European Signal Processing Conference, Bucharest, Romania;
    ISVLSI'2012 - IEEE Computer Society Annual Symposium on VLSI, University of Massachusetts, Amherst, USA;
    TSP'2012 - IEEE International Conference on Telecommunications and Signal Processing, Prague, Czech Republic;
    ICME'2012 - IEEE International Conference on Multimedia & Expo, Melbourne, Australia;
    ICCES'2011 - IEEE International Conference on Computer Engineering and Systems, Cairo, Egypt;
    TSP'2011 - IEEE International Conference on Telecommunications and Signal Processing, Budapest, Hungary;
    ICME'2011 - IEEE International Conference on Multimedia & Expo, Barcelona, Spain;
    ICME'2010 - International Conference on Multimedia & Expo, Singapure;
    ICME'2009 - International Conference on Multimedia & Expo, Cancun, Mexico;
    MUE'2009 - International Conference on Multimedia and Ubiquitous Engineering, Qingdao, China;
    ICME'2008 - International Conference on Multimedia & Expo, Hannover, Germany;
    PCS'2007 - 26th Picture Coding Symposium, Lisboa, Portugal;
    ICME'2007 - International Conference on Multimedia & Expo, Beijing, China;
    CSS'2004 - IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, Florida, USA;
    FPL'2003 - 13th International Conference on Field Programmable Logic and Applications, Lisbon, Portugal;
    ISCAS'2000 - IEEE International Symposium on Circuits and Systems, Geneva, Switzerland.
    National Conferences:
    REC'2013 - IX Jornadas sobre Sistemas Reconfiguráveis, Universidade de Coimbra, Coimbra, Portugal, 7-8 February, 2013
    REC'2012 - VIII Jornadas sobre Sistemas Reconfiguráveis, Instituto Superior de Engenharia de Lisboa , Lisboa, Portugal, 9-10 February, 2012
    REC'2011 - VII Jornadas sobre Sistemas Reconfiguráveis, Faculdade de Engenharia de Universidade do Porto, Portugal, 3-4 February, 2011
    REC'2010 - VI Jornadas sobre Sistemas Reconfiguráveis, Universidade de Aveiro/IEETA, Aveiro, Portugal;
    REC'2009 - V Jornadas sobre Sistemas Reconfiguráveis, Universidade Nova de Lisboa, Lisboa, Portugal;
    JETC'2008 - IV Jornadas de Engenharia de Electrónica e Telecomunicações e de Computadores, ISEL, Lisbon, Portugal;
    REC'2008 - IV Jornadas sobre Sistemas Reconfiguráveis, Universidade do Minho, Braga, Portugal.


Prizes and Awards:

Awarded with the following prizes and recognitions:

  • Best Paper Award, International Conference on Design and Architectures for Signal and Image Processing (DASIP'2013);
  • Quality Reviewer Award, IEEE International Conference on Multimedia & Expo (ICME'2013);
  • Stamatis Vassiliadis Best Paper Award, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'2011);
  • Outstanding Paper Award (Runner-Up), International Conference on High Performance Computing & Simulation (HPCS'2011);
  • Quality Reviewer Award, IEEE International Conference on Multimedia & Expo (ICME'2011);
  • Best Poster Award, International Conference on Design and Architectures for Signal and Image Processing (DASIP'2010);
  • Best Paper Award, Jornadas sobre Sistemas Reconfiguráveis (REC'2010);
  • Best Paper Award, Jornadas sobre Sistemas Reconfiguráveis (REC'2005).